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general description the MAX105 is a dual, 6-bit, analog-to-digital converter (adc) designed to allow fast and precise digitizing of in-phase (i) and quadrature (q) baseband signals. the MAX105 converts the analog signals of both i and q components to digital outputs at 800msps while achiev- ing a signal-to-noise ratio (snr) of typically 37db with an input frequency of 200mhz, and an integral nonlin- earity (inl) and differential nonlinearity (dnl) of ?.25 lsb. the MAX105 analog input preamplifiers feature a 400mhz, -0.5db, and a 1.5ghz, -3db analog input bandwidth. matching channel-to-channel performance is typically 0.04db gain, 0.1lsb offset, and 0.2 degrees phase. dynamic performance is 36.4db signal-to-noise plus distortion (sinad) with a 200mhz analog input sig- nal and a sampling speed of 800mhz. a fully differen- tial comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 10 16 clock cycles. in addition, the MAX105 provides lvds digital outputs with an internal 6:12 demultiplexer that reduces the out- put data rate to one-half the sample clock rate. data is output in two? complement format. the MAX105 oper- ates from a +5v analog supply and the lvds output ports operate at +3.3v. the data converter? typical power dissipation is 2.6w. the device is packaged in an 80-pin, tqfp package with exposed paddle, and is specified for the extended (-40? to +85?) tempera- ture range. for a lower-speed, 400msps version of the MAX105, please refer to the max107 data sheet. applications vsat receivers wlans test instrumentation communications systems features two matched 6-bit, 800msps adcs excellent dynamic performance 36.4db sinad at f in 200mhz and f clk 800mhz typical inl and dnl: ?.25lsb channel-to-channel phase matching: ?.2 channel-to-channel gain matching: ?.04db 6:12 demultiplexer reduces the data rates to 400mhz low error rate: 10 16 metastable states at 800msps lvds digital outputs in two? complement format MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ________________________________________________________________ maxim integrated products 1 ref i primary port i auxiliary port q primary port q auxiliary port i adc q adc max107 block diagram 19-2006; rev 0; 5/01 ordering information part temp. range pin-package MAX105ecs -40 c to +85 c 80-pin tqfp-ep pin configuration appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc , av cc i, av cc q and av cc r to agnd............-0.3v to +6v ov cc i and ov cc q to ognd ...................................-0.3v to +4v agnd to ognd ................................................... -0.3v to +0.3v p0i to p5i and a0i to a5i dready+, dready- to ogndi .............-0.3v to ov cc i+0.3v p0q to p5q, a0q to a5q dor+ and dor- to ogndq ................-0.3v to ov cc q+0.3v ref to agndr...........................................-0.3v to av cc r+0.3v differential voltage between ini+ and ini- ....................-2v, +2v differential voltage between inq+ and inq-.................-2v, +2v differential voltage between clk+ and clk- ...............-2v, +2v maximum current into any pin ...........................................50ma continuous power dissipation (t a = +70 c) 80-pin tqfp (derate 44mw/ c above +70 c)..................3.5w operating temperature range MAX105ecs .....................................................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) ..................................+300 c electrical characteristics (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) parameter symbol conditions min typ max units dc accuracy resolution res 6 bits integral nonlinearity (note 1) inl -1 0.2 1 lsb differential nonlinearity (note 1) dnl no missing codes guaranteed -1 0.25 1 lsb offset voltage v os (note 2) -1 0.25 1 lsb o ffset m atchi ng betw een ad c s om (note 2) -0.5 0.1 0.5 lsb analog inputs (ini+, ini-, inq+, inq-) input open-circuit voltage v aoc 2.4 2.5 2.6 v input open-circuit voltage matching (v ini+ - v in- ) - (v inq+ - v inq- ) 7.5 mv common mode input voltage range (note 3) v cm signal + offset w.r.t. agnd 1.85 3.05 v full-scale analog input voltage range (note 4) v fsr 0.76 0.8 0.84 v p-p input resistance r in 1.7 2 k ? input capacitance c in 1.5 pf input resistance temperature coefficient tcr in 150 ppm/ c full-power analog input bw fpbw -0.5db 400 mhz reference output reference output resistance r ref referenced to agndr 5 ? reference output voltage ref i source = 500 a 2.45 2.50 2.55 v
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier _______________________________________________________________________________________ 3 electrical characteristics (continued) (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) parameter symbol conditions min typ max units clock inputs (clk+, clk-) clock input resistance r clk clk+ and clk- to agnd 5 k ? clock input resistance temperature coefficient tcr clk 150 ppm/ c minimum clock input amplitude 500 mv p - p lvds outputs (p0i to p5i, p0q to p5q, a0i to a5i, a0q to a5q, dready+, dready-, dor+, dor-) differential output voltage ? v od ? 247 400 mv c hang e i n m ag ni tud e of ? v od ? betw een 0 and 1 s tates ?? v od ? 25 mv steady-state common mode output voltage v oc ( ss ) 1.125 1.375 v change in magnitude of v oc between 0 and 1 states ?? v oc ? 25 mv differential output resistance 80 160 ? short output together 2.5 output current short to ogndi = ogndq 25 ma dynamic specification differential 5.4 5.8 f in = 200.018mhz at -0.5db fs (note 9) single-ended 5.75 effective number of bits (note 8) enob f in = 400.134mhz at -0.5db fs differential 5.65 bits differential 35 37 f in = 200.018mhz at -0.5db fs (note 9) single-ended 36.7 signal-to-noise ratio (notes 10, 11) snr f in = 400.134mhz at -0.5db fs differential 36.5 db differential -44.5 -41 f in = 200.018mhz at -0.5db fs (note 9) single-ended -44.5 total harmonic distortion (note 11) thd f in = 400.134mhz at -0.5db fs differential -41 dbc differential 41 45 f in = 200.018mhz at -0.5db fs (note 9) single-ended 45 spurious-free dynamic range sfdr f in = 400.134mhz at -0.5db fs differential 41.5 db
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 4 _______________________________________________________________________________________ electrical characteristics (continued) (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) parameter symbol conditions min typ max units differential 34 36.4 f in = 200.018mhz at -0.5db fs (note 9) single-ended 36.1 signal-to-noise plus distortion ratio sinad f in = 400.134mhz at -0.5db fs differential 35.2 db two-tone intermodulation ttimd f in1 = 124.1660mhz, f in2 = 126.1260mhz at -7dbfs -52 dbc crosstalk between adcs xtlk f ini = 200.0180mhz, f inq = 210.0140mhz at -0.5db fs -70 db gain match between adcs gm (note 12) -0.3 0.04 +0.3 db phase match between adcs pm (note 12) -2 0.2 +2 deg metastable error rate less than 1 in 10 16 clock cycles power requirements analog supply voltage av cc_ av cc = av cc i = av cc q = av cc r5 5% v digital supply voltage ov cc_ ov cc i = ov cc q 3.3 10% v analog supply current i cc i cc = ai cc r + ai cc i + ai cc q + ai cc 250 320 ma output supply current oi cc oi cc = oi cc i + oi cc q 400 510 ma analog power dissipation p diss 2.6 w c om m on- m od e rej ecti on rati o cmrr v in_+ = v in_- = 0.1v (note 6) 40 60 db power-supply rejection ratio psrr av cc = av cc i = av cc q = av cc r = +4.75v to +5.25v (note 7) 40 57 db timing characteristics maximum sample rate f max 800 msps clock pulse width low t pwl 0.56 ns clock pulse width high t pwh 0.56 ns aperture delay t ad 100 ps aperture jitter t aj 1.5 ps rms clk-to-dready propagation delay t pd1 (note 13) 1.5 ns dready-to-data propagation delay t pd2 (notes 5, 13) 0 120 300 ps
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier _______________________________________________________________________________________ 5 note 1: nl and dnl is measured using a sine-histogram method. note 2: input offset is the voltage required to cause a transition between codes 0 and -1. note 3: numbers provided are for dc-coupled case. the user has the choice of ac-coupling, in which case, the dc input voltage level does not matter. note 4: the peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algorithm (e.g. fft). note 5: guaranteed by design and characterization. note 6: common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common- mode voltage expressed in db. note 7: measured with analog power supplies tied to the same potential. note 8: effective number of bits (enob) is computed from a curve-fit referenced to the theoretical full-scale range. note 9: the clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record. note 10: signal-to-noise-ratio (snr) is measured both with the other channel idling and converting an out-of-phase signal. the worst case number is presented. harmonic distortion components two through five are excluded from the noise. note 11: harmonic distortion components two through five are included in the total harmonic distortion specification. note 12: both i and q inputs are effectively tied together (e.g. driven by power splitter). signal amplitude is -0.5db fs at an input frequency of f in = 200.0180 mhz. note 13: measured with a differential probe, 1pf capacitance. electrical characteristics (continued) (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) parameter symbol conditions min typ max units dready duty cycle (notes 5, 13) 47 53 % lvds output rise-time t rdata 20% to 80% (notes 5, 13) 200 500 ps lvds output fall-time t fdata 20% to 80% (notes 5, 13) 200 500 ps any differential pair <65 ps lvds differential skew t skew1 any tw o lv d s outp ut si g nal s excep t d re ad y <100 ps dready rise-time t rdready 20% to 80% (notes 5, 13) 200 500 ps dready fall-time t fdready 20% to 80% (notes 5, 13) 200 500 ps primary port pipeline delay t pdp 5 clock cycles auxiliary port pipeline delay t pda 6 clock cycles
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 6 _______________________________________________________________________________________ typical operating characteristics (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, differential input at -0.5db fs, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0 20 40 60 80 100 120 140 8192-point fft, differential input MAX105 toc01 analog input frequency (mhz) amplitude (db fs) f in = 125.146mhz a in = -0.5db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 080 40 120 160 200 8192-point fft, differential input MAX105 toc02 analog input frequency (mhz) amplitude (db fs) f in = 124.999mhz a in = -0.5db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 0 140 70 210 280 350 420 8192-point fft, differential input MAX105 toc03 analog input frequency (mhz) amplitude (db fs) f in = 400.124mhz a in = -0.5db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 0 160 80 240 320 400 two-tone imd (8192-point record), differential input MAX105 toc04 analog input frequency (mhz) amplitude (db fs) f n1 = 124.166mhz f in2 = 126.126mhz a in = -7db fs f in1 f in2 40 0 10m 1g 10g sinad vs. analog input frequency, differential input 10 5 15 20 25 30 35 MAX105 toc06 analog input frequency (hz) amplitude (db) 100m -12db fs -6db fs -1db fs -20 -60 10m 1g 10g thd vs. analog input frequency, differential input -50 -55 -45 -40 -35 -30 -25 MAX105 toc07 analog input frequency (hz) amplitude (db) 100m -12db fs -1db fs -6db fs 55 10 10m 10g 1g 100m sfdr vs. analog input frequency, differential input 25 15 45 35 60 30 20 50 40 MAX105 toc08 analog input frequency (hz) amplitude (db) -12db fs -1db fs -6db fs -4 10m 10g 1g 100m full-power input bandwidth single-ended input 1 -2 -3 0 -1 MAX105 toc09 analog input frequency (hz) gain (db) 40 0 10m 1g 10g snr vs. analog input frequency, differential input 10 5 15 20 25 30 35 MAX105 toc05 analog input frequency (hz) amplitude (db) 100m -1db fs -6db fs -12db fs
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier _______________________________________________________________________________________ 7 -50 -46 -38 -42 -34 -10 -8 -7 -6 -5 -9 -4 -3 -2 -1 0 thd vs. analog input power, differential input MAX105 toc12 analog input power (db fs) thd (db) f in = 199.8535mhz 25 29 37 33 41 45 -40 10 -15 35 60 85 snr vs. temperature MAX105 toc14 temperature ( c) snr (db) f in = 199.8535mhz 24 28 36 32 40 -10 -8 -7 -6 -5 -9 -4 -3 -2 -1 0 snr vs. analog input power, differential input MAX105 toc10 analog input power (db fs) snr (db) f in = 199.8535mhz 24 28 36 32 40 -10 -8 -7 -6 -5 -9 -4 -3 -2 -1 0 sinad vs. analog input power, differential input MAX105 toc11 analog input power (db fs) sinad (db) f in = 199.8535mhz 38 44 42 40 46 48 50 -10 -6 -7 -9 -8 -5 -4 -3 -2 -1 0 sfdr vs. analog input power, differential input MAX105 toc13 analog input power (db fs) sfdr (db) f in = 199.8535mhz 32 34 38 36 40 42 -40 10 -15 35 60 85 sinad vs. temperature MAX105 toc15 temperature ( c) sinad (db) f in = 199.8535mhz -38 -42 -46 -50 -54 -40 10 -15 35 60 85 thd vs. temperature max toc16 temperature ( c) thd (db) f in = 199.8535mhz 35 39 47 43 51 55 -40 10 -15 35 60 85 sfdr vs. temperature MAX105 toc17 temperature ( c) sfdr (db) f in = 199.8535mhz 30 32 36 34 38 40 400 600 500 700 800 900 snr vs. clock frequency, differential input (-1db fs) MAX105 toc18 clock frequency (mhz) amplitude (db) f in = 202.346mhz typical operating characteristics (continued) (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, differential input at -0.5db fs, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c)
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 8 _______________________________________________________________________________________ 30 32 36 34 38 40 400 600 500 700 800 900 sinad vs. clock frequency, differential input (-1db fs) MAX105 toc19 clock frequency (mhz) amplitude (db) f in = 202.346mhz -55 -52 -46 -49 -43 -40 400 600 500 700 800 900 thd vs. clock frequency, differential input (-1db fs) MAX105 toc20 clock frequency (mhz) amplitude (db) f in = 202.346mhz 5.5 5.6 5.8 5.7 5.9 6.0 4.5 4.9 4.7 5.1 5.3 5.5 enob vs. analog supply voltage, differential input (-1db fs) MAX105 toc21 analog supply voltage (v) enob (bits) f in = 202.0761mhz 45 46 48 47 49 50 4.5 4.9 4.7 5.1 5.3 5.5 sfdr vs. analog supply voltage, differential input (-1db fs) MAX105 toc22 analog supply voltage (v) sfdr (db) f in = 202.0761mhz -0.30 -0.20 -0.10 0 0.10 0.20 0.30 016 8 243240485664 inl vs. digital output code MAX105 toc23 digital output code inl (lsb) -0.40 -0.20 0 0.20 0.40 0 163248 8 24405664 dnl vs. digital output code MAX105 toc24 digital output code dnl (lsb) 2.490 2.494 2.502 2.498 2.506 2.510 4.5 4.9 4.7 5.1 5.3 5.5 reference voltage vs. analog supply voltage max toc25 analog supply voltage (v) reference voltage (v) 200 220 260 240 280 300 4.5 4.9 4.7 5.1 5.3 5.5 analog supply current vs. analog supply voltage MAX105 toc26 analog supply voltage (v) analog supply current (ma) 200 220 260 240 280 300 -40 10 -15 35 60 85 analog supply current vs. temperature MAX105 toc27 temperature ( c) analog supply current (ma) typical operating characteristics (continued) (av cc = av cc i = av cc q = av cc r = +5v, ov cc i = ov cc q = +3.3v, agnd = agndi = agndq = agndr = 0, ogndi = ogndq = 0, f clk = 802.816mhz, differential input at -0.5db fs, c l = 1f to agnd at ref, r l = 100 ? 1% applied to digital lvds outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c)
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier _______________________________________________________________________________________ 9 pin name function 1, 20 t.p. test point. do not connect. 2 ref reference output 3av cc r analog reference supply. supply voltage for the internal bandgap reference. bypass to agndr with 0.01f in parallel with 47pf for proper operation. 4 agndr reference, analog ground. connect to agnd for proper operation. 5, 8 agndi i-channel, analog ground. connect to agnd for proper operation. 6 ini- i-channel, differential input. negative terminal. 7 ini+ i channel, differential input. positive terminal. 9av cc i i-channel, analog supply. supplies i-channel common-mode buffer, pre-amplifier and quantizer. bypass to agndi with 0.01f in parallel with 47pf for proper operation. 10 clk+ sampling clock input 11 clk- complementary sampling clock input 12 av cc q q-channel, analog supply. supplies q-channel common-mode buffer, pre-amplifier and quantizer. bypass to agndq with 0.01f in parallel with 47pf for proper operation. 13, 16 agndq q-channel, analog ground. connect to agnd for proper operation. 14 inq+ q-channel, differential input. positive terminal. 15 inq- q-channel, differential input. negative terminal. 17, 18 agnd analog ground 19 av cc analog supply. bypass to agnd with 0.01f in parallel with 47pf for proper operation. 21 a5q+ auxiliary output data bit 5 (msb), q-channel 22 a5q- complementary auxiliary output data bit 5 (msb), q-channel 23 p5q+ primary output data bit 5 (msb), q-channel 24 p5q- complementary primary output data bit 5 (msb), q-channel 25 a4q+ auxiliary output data bit 4, q-channel 26 a4q- complementary auxiliary output data bit 4, q-channel 27 p4q+ primary output data bit 4, q-channel 28 p4q- complementary primary output data bit 4, q-channel 29, 35 ov cc q q-channel outputs, digital supply. supplies q-channel output drivers and dor logic. bypass to ognd with 0.01f in parallel with 47pf for proper operation. 30, 36 ogndq q-channel outputs, digital ground. connect to designated digital ground (ognd) on pc board for proper operation. pin description
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 10 ______________________________________________________________________________________ pin name function 31 a3q+ auxiliary output data bit 3, q-channel 32 a3q- complementary auxiliary output data bit 3, q-channel 33 p3q+ primary output data bit 3, q-channel 34 p3q- complementary primary output data bit 3, q-channel 37 a2q+ auxiliary output data bit 2, q-channel 38 a2q- complementary auxiliary output data bit 2, q-channel 39 p2q+ primary output data bit 2, q-channel 40 p2q- complementary primary output data bit 2, q-channel 41 a1q+ auxiliary output data bit 1, q-channel 42 a1q- complementary auxiliary output data bit 1, q-channel 43 p1q+ primary output data bit 1, q-channel 44 p1q- complementary primary output data bit 1, q-channel 45 a0q+ auxiliary output data bit 0 (lsb), q-channel 46 a0q- complementary auxiliary output data bit 0 (lsb), q-channel 47 p0q+ primary output data bit 0 (lsb), q-channel 48 p0q- complementary primary output data bit 0 (lsb), q-channel 49 dor+ complementary lvds out-of-range bit 50 dor- lvds out-of-range bit 51 dready- complementary data-ready clock 52 dready+ data ready clock 53 p0i- complementary primary output data bit 0 (lsb), i-channel 54 p0i+ primary output data bit 0 (lsb), i-channel 55 a0i- complementary auxiliary output data bit 0 (lsb), i-channel 56 a0i+ auxiliary output data bit 0 (lsb), i-channel 57 p1i- complementary primary output data bit 1, i-channel 58 p1i+ primary output data bit 1, i-channel 59 a1i- complementary auxiliary output data bit 1, i-channel 60 a1i+ auxiliary output data bit 1, i-channel 61 p2i- complementary primary output data bit 2, i-channel pin description (continued)
detailed description the MAX105 is a dual, +5v, 6-bit, 800msps flash ana- log-to-digital converter (adc), designed for high- speed, high-bandwidth i&q digitizing. each adc (figure 1) employs a fully differential, wide bandwidth input stage, 6-bit quantizers and a unique encoding scheme to limit metastable states to typically one error per 10 16 clock cycles, with no error exceeding a maxi- mum of 1lsb. an integrated 6:12 output demultiplexer simplifies interfacing to the part by reducing the output data rate to one-half the sampling clock rate. the MAX105 outputs data in lvds two s complement for- mat. when clocked at 800msps, the MAX105 provides a typ- ical signal-to-noise plus distortion (sinad) of 36.4db with a 200mhz input tone. the analog input of the MAX105 is designed for differential or single-ended use with a 400mv full-scale input range. in addition, the MAX105 features an on-board +2.5v precision bandgap reference, which is scaled to meet the analog input full-scale range. principle of operation the MAX105 employs a flash or parallel architecture. the key to this high-speed flash architecture is the use of an innovative, high-performance comparator design. each quantizer and downstream logic translates the comparator outputs into 6-bit, parallel codes in two s complement format and passes them on to the internal 6:12 demultiplexer. the demultiplexer enables the adcs to provide their output data at half the sampling speed on primary and auxiliary ports. lvds data is available at speeds of up to 400mhz per output port. input amplifier circuits as with all adcs, if the input waveform is changing rapidly during conversion, effective number of bits (enob), signal-to-noise plus distortion (sinad), and MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ______________________________________________________________________________________ 11 pin name function 62 p2i+ primary output data bit 2, i-channel 63 a2i- complementary auxiliary output data bit 2, i-channel 64 a2i+ auxiliary output data bit 2, i-channel 65, 72 ov cc i i-channel outputs, digital supply. supplies i-channel output drivers and dready circuit. bypass to ognd with 0.01f in parallel with 47pf for proper operation. 66, 71 ogndi i-channel outputs, digital ground. connect to designated digital ground (ognd) on pc board for proper operation. 67 p3i- complementary primary output data bit 3, i-channel 68 p3i+ primary output data bit 3, i-channel 69 a3i- complementary auxiliary output data bit 3, i-channel 70 a3i+ auxiliary output data bit 3, i-channel 73 p4i- complementary primary output data bit 4, i-channel 74 p4i+ primary output data bit 4, i-channel 75 a4i- complementary auxiliary output data bit 4, i-channel 76 a4i+ auxiliary output data bit 4, i-channel 77 p5i- complementary primary output data bit 5, i-channel 78 p5i+ primary output data bit 5, i-channel 79 a5i- complementary auxiliary output data bit 5, i-channel 80 a5i+ auxiliary output data bit 5, i-channel pin description (continued)
MAX105 signal-to-noise ratio (snr) specifications will degrade. the MAX105 s on-board, wide-bandwidth input ampli- fiers (i&q) reduce this effect significantly, allowing pre- cise digitizing of fast analog data at high conversion rates. the input amplifiers buffer the input signal and allow a full-scale signal input range of 400mv (800mv p-p ). internal reference the MAX105 features an integrated, buffered +2.5v precision bandgap reference. this reference is internal- ly scaled to match the analog input range specification of 400mv. the data converter s reference output (ref) can source up to 500a. ref should be buffered, if used to supply external devices. lvds digital outputs the MAX105 provides data in two s complement format to differential lvds outputs. a simplified circuit schematic of the lvds output cells is shown in figure 2. all lvds outputs are powered from separate i-chan- nel ov cc i and q-channel ov cc q (q-channel) power supplies, which may be operated at +3.3v 10%. the dual, 6-bit, 800msps adc with on-chip, wideband input amplifier figure 1. MAX105 flash converter architecture ini- ini+ 2k ? clk+ av cc clk- p0i+/p0i- dready+/dready- dor+/dor- p5i+/p5i- a0i+/a0i- a5i+/a5i- p0q+/p0q- p5q+/p5q- a0q+/a0q- a5q+/a5q- 10k ? 10k ? cm buffer cm buffer reference primary data port p0i-p5i auxiliary data port a0i-a5i primary data port p0q-p5q auxiliary data port a0q-a5q i adc 1:2 ref MAX105 inq- inq+ 2k ? pre-amp q adc ref ref dor pre-amp MAX105 p0i+ - p5i+ a0i+ - a5i+ p0i- - p5i- a0i- - a5i- ov cc i ov cc i ov cc i 55 ? 55 ? figure 2. simplified lvds output model 12 ______________________________________________________________________________________
MAX105 lvds-outputs provide a typical 270mv volt- age swing around a common mode voltage of roughly +1.2v, and must be differentially terminated at the far end of each transmission line pair (true and comple- mentary) with 100 ? . out-of-range operation a single output pair (dor+, dor-) is provided to flag an out-of-range condition, if either the i or q channel is out-of-range, where out-of-range is above +fs or below -fs. it features the same latency as the adcs output data and is demultiplexed in a similar fashion. with a 800mhz system clock, dor+ and dor- are clocked at up to 400mhz. applications information single-ended analog inputs the MAX105 is designed to work at full-speed for both single-ended and differential analog inputs without sig- nificant degradation in its dynamic performance. both input channels i (ini+, ini-) and q (inq+, inq-) have 2k ? impedance and allow for ac- and dc-coupled input signals. in a typical dc-coupled single-ended configuration ( table 1), the analog input signals enter the analog input amplifier stages at the in-phase-input pins ini+/inq+, while the inverted phase input ini- /inq- pins are ac-coupled to agndi/agndq. single- ended operation allows for an input amplitude of 800mv p-p , centered around v ref . differential analog inputs to obtain +fs digital outputs with differential input drive (table 2), 400mv must be applied between ini+ (inq+) and ini- (inq-). midscale digital output codes occur when there is no voltage difference between ini+ (inq+) and ini- (inq-). for a -fs digital output code both in-phase (ini+, inq+) and inverted input (ini-, inq-) must see -400mv. single-ended to differential conversion using a balun an rf balun (figure 3) provides an excellent solution to convert a single-ended signal to a fully differential sig- nal, required by the MAX105 for optimum performance. at higher frequencies, the MAX105 provides better sfdr and thd with fully differential input signals over single-ended input signals. in differential input mode, even-order harmonics are suppressed and each input requires only half the signal-swing compared to single- ended mode. clock input the MAX105 features clock inputs designed for either single-ended or differential operation with very flexible input drive requirements. the clock inputs (ac- or dc- coupled) provide a 5k ? input impedance to av cc /2 MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ______________________________________________________________________________________ 13 in-phase inputs (ini+, inq+) inverted inputs (ini-, inq-) out-of-range bit (dor+, dor-) output code > +400mv + v ref ac coupled to agnd_ 1 011111 +400mv - 0.5lsb + v ref ac coupled to agnd_ 0 011111 0v + v ref ac coupled to agnd_ 0 000000/111111 -400mv + 0.5lsb + v ref ac coupled to agnd_ 0 100000 < -400mv + v ref ac coupled to agnd_ 1 100000 table 1. digital output codes corresponding to a dc-coupled single-ended analog input in-phase inputs (ini+, inq+) inverted inputs (ini-, inq-) out-of-range bit (dor+, dor-) output code >+200mv + v ref <-200mv + v ref 1 011111 +200mv - 0.25lsb + v ref -200mv + 0.25lsb + v ref 0 011111 0v + v ref 0v + v ref 0 000000/111111 -200mv + 0.25lsb + v ref +200mv - 0.25lsb + v ref 0 100000 <-200mv + v ref >+200mv + v ref 1 100000 table 2. digital output codes corresponding to a dc-coupled differential analog input
MAX105 and are internally buffered with a preamplifier to ensure proper operation of the converter even with small- amplitude sine-wave sources. the MAX105 was designed for single-ended, low-phase noise sine wave clock signals with as little as 500mv p-p amplitude (-2dbm). single-ended clock (sine-wave drive) excellent performance is obtained by ac- or dc-cou- pling a low-phase noise sine-wave source into a single clock input ( figure 4). essentially, the dynamic perfor- mance of the converter is unaffected by clock-drive power levels from -2dbm (500mv p-p clock signal ampli- tude) to +10dbm (2v p-p clock signal amplitude). the MAX105 dynamic performance specifications are determined by a single-ended clock drive of -2dbm (500mvp-p clock signal amplitude). to avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dbm. differential clock (sine-wave drive) the advantages of differential clock drive (figure 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. refer to single-ended clock inputs (sine-wave drive) for proper input amplitude requirements. lvds, ecl and pecl clock the innovative input architecture of the MAX105 clock also allows these inputs to be driven by lvds-, ecl-, or pecl-compatible input levels, ranging from 500mv p-p to 2v p-p (figure 6). timing requirements the MAX105 features a 6:12 demultiplexer, which reduces the output data rate (including dready and dor signals) to one-half of the sample clock rate. the dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 14 ______________________________________________________________________________________ agnd agnd b 0 0 180 0 d c a signal source 50 ? *termination of the unused input/output (with 50 ? to agnd) on a balun is recommended in order to avoid unwanted reflections. clk+, ini+, inq+ clk-, ini-, inq- 100pf 100pf 50 ? 50 ? agnd 50 ? * figure 3. single-ended to differential conversion using a balun agnd agnd from signal source clk+, ini+, inq+ clk-, ini-, inq- 100pf 100pf 50 ? figure 4. single-ended clock input with ac-coupled input drive (clk, ini, inq) figure 5. differential ac-coupled input drive (clk, ini, inq) agnd agnd 50 ? transmission lines to 50 ? -terminated signal source or balum clk+, ini+, inq+ clk-, ini-, inq- 100pf 100pf 50 ? 50 ? 50 ? transmission lines lvds line driver signal source input clk+, ini+, inq+ clk-, ini-, inq- 100pf 100pf 100 ? figure 6. lvds input drive (clk, ini, inq)
demultiplexed outputs are presented in dual 6-bit two s complement format with two consecutive samples in the primary and auxiliary output ports on the rising edge of the data ready clock. the auxiliary data port always contains the older sample. the primary output always contains the most recent data sample, regard- less of the dready clock phase. figure 7 shows the timing and data alignment of the auxiliary and primary output ports in relationship with the clk and dready signals. data in the primary port is delayed by five clock cycles while data in the auxiliary port is delayed by six clock cycles. typical i/q application quadrature amplitude modulation (qam) is frequently used in digital communication systems to increase channel capacity. a qam signal is modulated in both amplitude and phase. with a demodulator, this qam signal gets downconverted and separated in its in- phase (i) and quadrature (q) components. both i&q channels are digitized by an adc at the baseband level in order to recover the transmitted information. figure 8 shows a typical application circuit to directly tune l-band signals to baseband, incorporating a direct conversion tuner (max2108) and the MAX105 to digitize i&q channels with excellent phase- and gain- matching. a front-end l-c filter is required for anti-alias- ing purposes. MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ______________________________________________________________________________________ 15 figure 7. output timing relationship between clk and dready signals and primary/auxiliary output ports clk+ clk- dready + dready - auxiliary port data primary port data t pwh t pwl t pd1 t pd2 note: the latency to the primary port is five clock cycles, the latency to the auxiliary port is six clock cycles. both primary and auxiliary data ports are updated on the rising edge of the dready+ clock. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n n+8 n+10 n+2 n+6 n+4 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample MAX105 adcs sample on the rising edge of clk+ clk dready auxiliary data port primary data port dready- dready+ n+14 n+15 n+16 n+17 n+18 n+19 n+9 n+11 n+3 n+1 n+7 n+5 MAX105
MAX105 grounding, bypassing, and board layout grounding and power supply decoupling strongly influ- ence the MAX105 s performance. at 800mhz clock fre- quency and 6-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, ground connections, and adversely influence the dynamic performance of the adc. in addition, the i&q inputs may crosstalk through poorly designed decou- pling circuits. therefore, closely follow the grounding and power-supply decoupling guidelines in figure 9. maxim strongly recommends using a multilayer printed circuit board (pc board) with separate ground and power supply planes. since the MAX105 has separate analog and digital ground connections (agnd, agndi, agndq, agndr, ogndi, and ogndq, respectively). the pc board should feature separate sections desig- nated to analog (agnd) and digital (ognd), connect- ed at only one point. digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. high-speed signals, including clocks, analog inputs, and digital outputs, should be routed on 50 ? microstrip lines, such as those employed on the MAX105ev kit. the MAX105 has separate analog and digital power- supply inputs: av cc = +5v 5%: power supply for the analog input section of the clock circuit. av cc i = +5v 5%: power supply for the i-channel common-mode buffer, pre-amp and quantizer. av cc q = +5v 5%: power supply for the q-chan- nel common-mode buffer, pre-amp and quantizer. av cc r = +5v 5%: power supply for the on-chip bandgap reference. ov cc i = +3.3v 10%: power supply for the i-chan- nel output drivers and dready circuitry. ov cc q = +3.3v 10%: power supply for the q-channel output drivers and dor circuitry. all supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the pc board. for best performance, bypass all power sup- dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 16 ______________________________________________________________________________________ 2k ? av cc dready+/dready- dor+/dor- 10k ? 10k ? cm buffer pre-amp nyquist filter from previous stage quadrature demodulator max2108 cm buffer reference primary data port p0i-p5i auxiliary data port a0i-a5i primary data port p0q-p5q auxiliary data port a0q-a5q i adc 1:2 d s p ref 2k ? pre-amp q adc ref dor lo 90 nyquist filter figure 8. typical i/q application
plies to the appropriate ground with a 10f tantalum capacitor, to filter power supply noise, in parallel with a 0.1f capacitor. a combination of 0.01f in parallel with high quality 47pf ceramic chip capacitor located very close to the MAX105 device filters high frequency noise. a properly designed pc board (see MAX105ev kit data sheet) allows the user to connect all analog supplies and all digital supplies together thereby requiring only two separate power sources. decoupling av cc , av cc i, av cc q and av cc r with ferrite-bead suppressors prevents further crosstalk between the individual analog supply pins thermal management the MAX105 is designed for a thermally enhanced 80- pin tqfp package, providing greater design flexibility, increased thermal efficiency and a low thermal junc- tion-case ( jc) resistance of 1.26 c/w. in this pack- MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ______________________________________________________________________________________ 17 av cc q av cc agndr agnd agndi agndq av cc q av cc agnd agndq agndi agndr av cc i pc board av cc pc board ov cc pc board agnd ferrite-bead suppressors pc board ognd av cc r av cc r av cc i ov cc q ov cc q ogndq ogndq ogndi ogndi ov cc i ov cc i, ov cc q ov cc i ov cc q ov cc q ogndq ogndq ogndi ogndi ov cc i ov cc i note: locate all 47pf and 10nf capacitors, which decouple av cc i, av cc q, av cc r, ov cc i, and ov cc q as close as possible to the chip. it is also recommended to connect all analog ground connections to a common analog ground plane and all digital ground connections to one common digital ground plane on the pc board. a similar technique can be used for all analog and digital power supplies. av cc = av cc i = av cc q = av cc r = +5v 5% ov cc i = ov cc q = +3.3v 10% 10nf 47pf 4 x 10nf 10nf 47pf 10 f 10nf 10 f 10nf 10nf 47pf 10nf 10nf 10nf 10nf 10nf 47pf 47pf 47pf 47pf 47pf MAX105 figure 9. MAX105 decoupling, bypassing and grounding
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 18 ______________________________________________________________________________________ age, the data converter die is attached to an exposed pad (ep) leadframe using a thermally conductive epoxy. the package is molded in a way, that this lead- frame is exposed at the surface, facing the printed cir- cuit board (pc board) side of the package (figure 10). this allows the package to be attached to the pc board with standard infrared (ir) flow soldering techniques. a specially created land pattern on the pc board, match- ing the size of the ep (7.5mm x 7.5mm) does not only guarantee proper attachment of the chip, but can also be used for heat-sinking purposes. designing thermal vias* into the land area and implementing large ground planes in the pc board design, further enhance the thermal conductivity between board and package. to remove heat from an 80-pin tqfp package efficiently, an array of 6 x 6 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) is required. note: efficient thermal management for the MAX105 is strongly depending on pc board and circuit design, component placement, and installation. therefore, exact performance figures cannot be provided. however, the MAX105ev kit exhibits a typical ja of 18 c/w. for more information on proper design tech- niques and recommendations to enhance the thermal performance of parts such as the MAX105, please refer to amkor technology s website at www.amkor.com. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nulli- fied. the static linearity parameters for the MAX105 are measured using the sine-histogram method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step-width and the ideal value of 1lsb. a dnl error specification of greater than -1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter and delay aperture uncertainties affect the dynamic performance of high-speed converters. aperture jitter, in particular, directly influences snr and limits the maximum slew rate (dv/dt) that can be digitized without significant error. aperture jitter limits the snr performance of the adc, according to the following relationship: snr db = 20 x log 10 [1 / (2 x x f in x t aj[rms] )], where f in represents the analog input frequency and t aj is the rms aperture jitter. the MAX105 s innovative die copper trace, 1oz. top layer ground plane (agnd) ground plane agnd, dgnd power plane thermal land copper plane, 1oz. 6 x 6 array of thermal vias thermal land copper plane, 1oz. exposed pad expoxy bonding wire 80-pin tqfp package with exposed pad copper trace, 1oz. pc board MAX105 figure 10. MAX105 exposed pad package cross-section *connects the land pattern to internal or external copper planes.
clock design limits aperture jitter to typically 1.5ps rms . figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken ( figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n-bits): snr max[db] = 6.02 db x n + 1.76 db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter (see aperture uncertainties ). snr is computed by tak- ing the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first four harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency, amplitude, and sampling rate relative to an ideal adc s quantization noise. for a full-scale input enob is computed from: enob = (sinad - 1.76 db ) / 6.02 db total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order har- monics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental to the rms value of the next largest spurious component, excluding dc offset. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -7db full-scale and their envelope peaks at -1db full-scale. chip information transistor count: 12,286 thd x v v v v v =+++ 20 2 2 3 2 4 2 5 2 1 2 log ( ) / ) MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier ______________________________________________________________________________________ 19 clk+ analog input sampling instant t aw t ad t aj clk- t aw : aperture width t aj : aperture jitter t ad : aperture delay MAX105 figure 11. aperture timing
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier 20 ______________________________________________________________________________________ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 a5i+ a5i- p5i+ p5i- a4i+ a4i- p4i+ p4i- ov cc i ogndi a3i+ 60 a1i+ a1i- p1i+ p1i- a0i+ a0i- p01+ p01- dready+ dready- dor- dor+ p0q- p0q+ a0q- a0q+ p1q- p1q+ a1q- a1q+ t.p. ref av cc r agndr agndi ini- ini+ agndi av cc i clk+ clk- av cc q agndq inq+ inq- agndq agnd agnd av cc t.p. 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a3i- p3i+ p3i- ogndi ov cc i 64 63 62 61 a2i+ a2i- p2i+ p2i- a5q+ a5q- p5q+ p5q- a4q+ a4q- p4q+ p4q- ov cc q ogndq a3q+ a3q- p3q+ p3q- ov cc q ogndq 37 38 39 40 a2q+ a2q- p2q+ p2q- MAX105 pin configuration
MAX105 dual, 6-bit, 800msps adc with on-chip, wideband input amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information

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